Senior Verification Engineer – ASIC (2 Positions)

Senior ASIC verification role requiring 8-15 years of hands-on block, subsystem and chip-top verification. The incumbent will develop SystemVerilog and UVM environments and tests, work on mixed-signal devices, implement RAL and functional and code coverage, run gate-level simulations across PVT corners and support DFT and ATPG simulations. Scripting in Perl, Python or Shell, collaboration with analog and architecture teams, FPGA-based validation, lab bring-up and customer-debug support are also required. This is a full-time work-from-office role in Bengaluru.

• Develop SystemVerilog and UVM environments and tests.
• Work on mixed-signal devices.
• Implement RAL and functional and code coverage.
• Run gate-level simulations across PVT corners.
• Support DFT and ATPG simulations.
• Scripting in Perl, Python or Shell.
• Collaboration with analog and architecture teams.
• FPGA-based validation.
• Lab bring-up and customer-debug support.

• 8-15 years of hands-on block, subsystem and chip-top verification.
• This is a full-time work-from-office role in Bengaluru.

• SystemVerilog
• UVM
• RAL
• functional coverage
• code coverage
• gate-level simulations
• DFT
• ATPG
• Perl