Senior Verification Engineer – ASIC (2 Positions)

Senior ASIC verification role requiring 8-15 years of hands-on block, subsystem and chip-top verification.

• Develop SystemVerilog and UVM environments and tests, work on mixed-signal devices, implement RAL and functional and code coverage, run gate-level simulations across PVT corners and support DFT and ATPG simulations.
• Scripting in Perl, Python or Shell, collaboration with analog and architecture teams, FPGA-based validation, lab bring-up and customer-debug support.
• This is a full-time work-from-office role in Bengaluru.

• Education: BE / BTech / ME / MTech in Electronics, Electrical or a related discipline

• ASIC Verification
• SystemVerilog
• UVM
• Mixed Signal
• RAL
• Functional Coverage
• Code Coverage
• Gate Level Simulation
• DFT