Senior Staff - SOC RTL Design Engineer (MCU)

About TYLsemi, Inc.

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package

Thats what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.

This isnt a nice-to-have. Its the critical path.

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moores Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - theyre all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: Were entering the market at exactly the moment when every major AI/HPC player needs what were building, and their alternatives are disappearing.

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Were not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. Were building to win.

• Ownership mindset. Youre not here to execute someone elses roadmap. Youre here to define it.
• Bias for action. We move fast. Analysis paralysis doesnt fly here.
• Deep technical expertise. This is hard engineering. We need people whove shipped real silicon and debugged real hardware.
• Low ego, high standards. We dont care about titles or politics. We care about results.

If youre reading this, youre probably comfortable. You have a good job at a stable company with all the benefits.

Were asking you to walk away from that and bet on us.

Heres why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what were building.
• The team has done this before. Weve built and exited semiconductor companies at scale. This isnt our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. Youre not optimizing someones ad click-through rate. Youre building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if youre the kind of person who wants to take the shot, wed love to talk.

READY TO JOIN

Role Overview

We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targeting AI, HPC, and Networking applications . This role requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on quality, performance, and first-time silicon success .

What You ll Do

• Specify and own the reset sequencing architecture. Own the secure boot and fuse micro architecture and design.

• Coordinate with the subsystem leads on reference clock distribution, clock-domain crossing points at subsystem interfaces.

• Collaborate with the firmware team to define the hardware/software interface: interrupt controller, timer, UART/JTAG debug port, and any DMA or mailbox channels

• Own the clock-gating implementation strategy: coarse-grain vs. fine-grain gating, ICG cell selection, and sign-off methodology for dynamic power reduction.

• Define the chip-level power-domain plan: which blocks share supplies, where level-shifters and isolation cells are required, and how power states map to the PCIe and UCIe link power management protocols.

• Own the on-chip power management logic: power-state machine, supply sequencing, voltage regulator integration, and the firmware interface for runtime power control.

• Drive power intent (UPF/CPF) authoring and sign-off, coordinating with physical design team on power-domain floorplan, always-on routing, and isolation verification.

• Own the embedded management processor subsystem: processor integration, on-chip SRAM and ROM sizing, boot sequence, fuse and OTP interface, and the firmware execution environment.

• Define the management register map: the address space through which firmware configures operating modes, reads telemetry, controls power states, and manages DFT operations.

• Specify thermal monitoring integration: on-die temperature sensor placement, readout path to the management processor, and thermal throttling hooks.

What We re Looking For

• 10+ years of digital IC design, with at least 5 years owning chip infrastructure - clocking, power management, reset or DFT - at block-lead or subsystem-owner level.

• Familiarity with embedded microcontroller integration: memory maps, boot ROM, interrupt controllers, and firmware bring-up at the hardware level.

• Experience with reset-domain architecture and reset synchronizer design in multi-power-domain chips.

• Strong SystemVerilog skills for infrastructure RTL: clock-gating cells, power FSMs, scan-enable muxing, and BIST controllers.
• BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Good to Have

• Background integrating a RISC-V or ARM Cortex-M class processor as a management/configuration engine in a non-CPU chiplet.

• Exposure to hardware security: secure boot, anti-tamper fuse programming, or related infrastructure.