Senior Staff - SoC Architect

We are seeking an experienced Senior Staff - SoC Architect with 8+ years of expertise in SoC architecture, microarchitecture development, RTL design, low-power methodologies, and post-silicon debug. The candidate will drive end-to-end SoC design activities, collaborate with cross-functional teams, and provide technical leadership to ensure successful silicon development and product delivery.

Your role

Key responsibilities in your new role

• Define and develop SoC architecture and microarchitecture for complex semiconductor products.
• Design and implement RTL using Verilog/System Verilog.
• Architect and optimize low-power solutions utilizing UPF methodologies.
• Develop and review clock, reset, power, DMA, and interconnect architectures.
• Perform and analyze CDC (Clock Domain Crossing), Lint, CLP (Convergence Low Power), and PTPX power analysis.
• Ensure compliance with AMBA protocols and industry-standard design practices.
• Collaborate closely with Verification, Software, Validation, DFT, Physical Design, PSVP, and System teams throughout the product lifecycle.
• Lead silicon bring-up, post-silicon validation, debugging, and root-cause analysis.
• Drive design reviews, architecture reviews, and technical decision-making.
• Mentor junior engineers and provide technical guidance across the design team.
• Support implementation teams in achieving performance, power, and area (PPA) targets.
  
  

Your profile

Qualifications And Skills To Help You Succeed

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of hands-on experience in SoC Architecture, Microarchitecture, RTL Design, and SoC Development using Verilog/SystemVerilog.
• Strong expertise in SoC Architecture & Microarchitecture, including clock, reset, power, DMA, and interconnect architecture.
• Deep understanding of AMBA protocols (AXI, AHB, APB) and complex SoC integration.
• Proven experience in Low-Power Design Methodologies, including UPF, CLP, power intent definition, and low-power architecture implementation.
• Proficiency in CDC, Lint, CLP, and Prime Time PX (PTPX) Power Analysis with strong design quality and signoff understanding.
• Extensive experience in RTL Design, Debug, Silicon Bring-up, Post-Silicon Validation, and Root Cause Analysis.
• Knowledge of DFT methodologies, physical design constraints, and performance, power, and area (PPA) optimization techniques.
• Exposure to Emulation, FPGA Prototyping, Pre-Silicon Validation Platforms (PSVP), and system-level validation environments.
• Strong understanding of Design Review, Quality Assurance, and Design Verification processes.
• Demonstrated ability to collaborate effectively with cross-functional teams including Verification, Software, Validation, DFT, Physical Design, and System Engineering.
• Proven Technical Leadership and Project Execution experience, including mentoring junior engineers, driving architecture and design reviews, and leading complex SoC development programs.
• Excellent analytical, problem-solving, communication, and stakeholder management skills
  
  

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in

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