Senior Staff Foundation IP Engineer (Arithmetic/DSP)

Job Summary

There is energy here energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

A successful candidate will join a team designing and developing Lattice FPGA software tools at Penang. The candidate will contribute to research, design and development of FPGA Foundation IP and IP Catalog tooling. The candidate is expected to work closely with cross-functional teams to plan and execute Lattice FPGA software release cycle including requirement analysis, feature scoping, development, testing and validation. The candidate also will be responsible for maintaining existing software product tools and develop improvement plan to increase the test coverage to achieve high product quality.

Key Responsibilities

• Design and implement DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units targeted for integration into FPGA fabric.
• Develop RTL (VHDL/Verilog/SystemVerilog) for DSP hard macros and programmable DSP slices.
• Perform functional simulation and timing analysis to ensure correctness and performance targets are met.
• Engage with software and tools teams to ensure DSP IP is correctly modeled in simulation libraries and synthesis flows.

Required Qualifications

• Bachelor's or Masters degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline.
• 8 or more years of experience in IP design or ASIC/FPGA engineering.
• Strong proficiency in RTL design using Verilog, VHDL, or SystemVerilog.
• Working experience in DSP theory and algorithms: filtering, FFT, fixed-point arithmetic, sample-rate conversion.

Preferred Qualifications

• Experience with functional verification methodologies (SystemVerilog Assertions, formal verification).
• Familiarity with synthesis and static timing analysis tools (Synopsys Design Compiler, PrimeTime, Radiant, Quartus or equivalent).
• Working knowledge of FPGA architectures and programmable DSP slice design.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India.

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