Senior Staff Engineer / Technical Lead - DFT

Position: Senior Staff Engineer / Technical Lead - DFT

Cyient Semiconductor | Bangalore / Hyderabad

Join Cyient Semiconductor and be part of building next-generation SoCs powering AI, Automotive, Networking, Data Center, Consumer, and Industrial applications.

We are looking for a highly experienced Senior Staff Engineer / Technical Lead - Design for Test (DFT) who can drive end-to-end DFT architecture, implementation, and signoff for complex SoC programs across advanced technology nodes.

Position: Senior Staff Engineer / Technical Lead - DFT

Location: Bangalore / Hyderabad

Experience: 6-15 Years

Key Responsibilities

• Lead end-to-end DFT implementation for complex SoCs and IPs.
• Define and drive DFT architecture, test strategy, and testability requirements.
• Own Scan Insertion, ATPG, Compression, MBIST, LBIST, Boundary Scan (JTAG), and diagnosis activities.
• Collaborate closely with Design, Physical Design, STA, Verification, and Silicon Validation teams.
• Drive DFT planning from RTL to silicon bring-up and production ramp.
• Develop and review DFT specifications, implementation guidelines, and signoff methodologies.
• Ensure DFT quality metrics including fault coverage, pattern count optimization, and test time reduction.
• Debug DFT-related issues during implementation, validation, and manufacturing stages.
• Interface with customers and stakeholders for technical reviews and project execution.
• Mentor and guide junior engineers while providing technical leadership to DFT teams.

Required Technical Skills

DFT Expertise

• Strong experience in:
• Scan Architecture & Scan Insertion
• ATPG
• Scan Compression
• MBIST
• LBIST
• JTAG / Boundary Scan
• Memory Repair & Redundancy Analysis
• Fault Simulation
• Silicon Debug & Failure Analysis

Tool Expertise

Hands-on experience with one or more industry-leading DFT tool suites:

Siemens Tessent

• Tessent Scan
• Tessent ATPG
• Tessent MBIST
• Tessent Diagnosis

Synopsys

• DFT Compiler
• TestMAX ATPG
• TestMAX Diagnosis

Cadence

• Modus DFT Solution

Additional Skills

• Strong understanding of SoC Architecture and RTL Design.
• Experience with Verilog/SystemVerilog.
• Good understanding of low-power DFT methodologies.
• Knowledge of STA, Timing Closure, and Physical Design constraints related to DFT.
• Experience with advanced technology nodes such as 16nm, 7nm, 5nm, 3nm FinFET technologies is highly desirable.
• Exposure to IEEE standards such as JTAG, IJTAG, and IEEE 1500.
• Experience working with global customers and distributed engineering teams.

Preferred Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Microelectronics, Electrical Engineering, or related fields.
• Proven track record of leading successful SoC tape-outs.
• Strong problem-solving, leadership, and stakeholder management skills.

Why Join Cyient Semiconductor?

Work on cutting-edge semiconductor products and advanced technology nodes.
Opportunity to lead high-impact DFT programs for global customers.
Collaborative engineering culture with strong career growth opportunities.
Exposure to next-generation AI, Automotive, Networking, and HPC designs.

Interested?

Share your updated CV to: [email removed]