Senior Staff Engineer, Design Verification

We are looking for a motivated and talented Digital Design Verification Engineer to join our team in creating next-generation Power management solutions.

Job Responsibilities

• Define and own verification plans, methodologies, and coverage strategies for complex SoC designs
• Architect and implement verification environments from scratch and enhance existing frameworks
• Drive block-level, subsystem-level, and full-chip verification
• Build Agents, sequences, drivers, monitors, and scoreboards as part of automation.
• Integrate industry-standard VIPs, create custom transactor.
• Lead end2end verification, including: Gate level simulations and debugs, coverage analysis and closure, regression, triage failures, and ensure quality sign-off
• Mentor junior and mid-level verification engineers
• Act as technical lead or owner for key verification deliverables Qualifications

• Bachelors degree in Electrical Engineering or equivalent practical experience.
• Overall 12+ years of experience with verification methodology such as universal verification methodology (UVM).
• Experience with industry-standard simulators, revision control systems, and regression systems.
• Experience with Architecting block the full verification lifecycle.
• Excellent problem solving and communication skills.
• Construct testbenches components like scoreboard, agents, sequencers, and monitors
• Debugging RTL and Gate simulations and working with cross functionals team to verify fixes
• Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up
• Experience developing and maintaining verification testbenches, test cases, and test environments.
• Understanding of SoC architecture and functionality, Mixed signal designs.
• Good knowledge of analog components : ADC, DAC, PLL, Oscilators and PI controllers.
• Passion for learning and engineering great solutions
• Proven written and verbal communication skills that demonstrate clarity of thought and conviction
• Working knowledge of one or more scripting languages (Perl, Python) and ability to use them to automate/accelerate verification and analysis tasks
• Experience of directed and constrained random verification methodology Good knowledge in UVM, Verilog, SV, C/C++, Shell, Python
• Strong debug, logical thinking and analytical skills
  
  Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.