Senior Staff Digital Design Engineer

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Staff Digital Design Engineer based in the United States.

This is a senior technical leadership opportunity focused on the design of next-generation digital subsystems for advanced RAIN RFID reader integrated circuits. You will lead digital design activities across the full semiconductor development lifecycle, from architecture and RTL through tapeout, silicon bring-up, and validation. The role combines hands-on engineering with technical leadership across digital, analog, RF, verification, physical design, and CAD/EDA disciplines. You will contribute to complex mixed-signal architectures, including digital control loops, calibration engines, and interface logic. You will also help strengthen ASIC/SoC methodologies and design flows to improve future development efficiency. This is an opportunity to shape innovative connectivity technology while mentoring engineers and influencing product direction.

Accountabilities: Lead digital design for next-generation RAIN RFID reader ICs, taking ownership from architecture and micro-architecture through RTL implementation, tapeout, and post-silicon validation.

Develop detailed micro-architectures, executable models, and RTL for complex digital and mixed-signal subsystems.

Partner with chip architects and RF/analog engineers to define and implement advanced mixed-signal architectures, including control loops, calibration engines, and analog IP interfaces.

Collaborate with verification and physical design teams to achieve robust functionality, timing closure, signal integrity, and production-ready silicon.

Define and implement DFT strategies, including scan insertion, BIST, boundary scan, and related test methodologies for mixed-signal IC designs.

Work with CAD/EDA engineering teams to improve ASIC/SoC design flows, methodologies, automation, and engineering best practices.

Enhance existing products through new functionality, performance improvements, and power optimizations.

Support post-silicon bring-up and debugging by correlating RTL and simulation results with laboratory measurements and silicon behavior.

Provide technical leadership across multidisciplinary engineering teams, drive complex workstreams, mentor engineers, and communicate design decisions effectively.

Requirements

Bachelor’s degree in Computer Engineering or a related technical discipline, with 12+ years of relevant experience; alternatively, 8+ years with a master’s degree or 5+ years with a PhD.

12+ years of hands-on RTL design experience, including at least 2–3 complete tapeout cycles, preferably involving mixed-signal or RF-integrated ICs.

Strong expertise in digital logic design, micro-architecture, synthesis, timing closure, and semiconductor design methodologies.

Advanced proficiency in Verilog and SystemVerilog for RTL development, behavioral modeling, and verification.

Strong understanding of CDC analysis, clock gating, low-power design methodologies such as UPF/CPF, and static timing analysis.

Experience with UVM-based verification, functional coverage, assertion-based verification, and DFT methodologies including scan, MBIST, and ATPG.

Scripting experience with Python, Perl, UNIX shell, or similar tools for design automation and engineering productivity.

Demonstrated ability to lead complex technical initiatives and mentor junior or mid-level engineers.

Strong communication and collaboration skills, with the ability to work effectively across digital, analog, RF, physical design, CAD/EDA, and systems engineering teams.

A strong problem-solving mindset and the ability to balance hands-on technical execution with broader architectural and product considerations.

Benefits

Base salary: $158,700–$238,100 USD across the United States, with individual offers determined by factors including role complexity, responsibilities, experience, skills, and market conditions.

Additional compensation: Eligibility for merit increases, annual bonuses, and stock awards based on role and individual performance.

Retirement: 401(k) plan with company matching.

Healthcare: Access to comprehensive healthcare benefits for U.S.-based employees.

Flexible work: Remote-eligible position in the United States, with a collaborative environment designed to support flexible working arrangements.

Paid time off: Open PTO policy designed to support work-life balance.

Professional environment: A culture centered on innovation, openness, collaboration, teamwork, and meaningful technological impact.

Career growth: Opportunities to influence engineering methodologies, mentor other engineers, and contribute to advanced semiconductor technology.

Inclusive workplace: Commitment to equal opportunity, diversity, inclusion, and reasonable workplace accommodations.

Work authorization: The position is U.S.-based and may be subject to U.S. export-control requirements.

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