Senior Silicon Digital Design Engineer, Core IP

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
• Experience with ASIC design methodologies for clock domain checks and reset checks.
  
  

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
• Experience implementing machine learning accelerators or camera ISP image processing IP or other multimedia IPs such as display or video codec.
• Proficient in scripting languages, C/C++ programming and software design skills.
• Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
  
  

About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first-party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration.
• Define and develop RTL implementations that meet power, performance and area goals.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
• Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .