Senior RTL Engineer

Key Responsibilities

Micro-Architecture & RTL Development

Design high-performance, low-latency PCIe controller logic and pipeline architectures.

Author detailed, clear micro-architectural specifications for hardware modules.

Implement clean, synthesizable RTL using SystemVerilog or Verilog.

PPA Optimization

Optimize designs to achieve best-in-class Performance, Power, and Area (PPA).

Architect efficient buffer management, flow control, and clock-gating strategies.

Execute structural changes to meet strict target frequencies and area constraints.

Design Quality & Sign-Off

Run and resolve Static Verification checks including Lint and CDC/RDC analysis.

Ensure design code strictly complies with industry-standard methodology guidelines.

Collaborate with Physical Design engineers to close synthesis and timing constraints

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Workflow Automation & AI Innovation

Develop scripts (Python, Tcl, Perl) to automate front-end design procedures.

Evaluate and integrate AI-assisted coding and EDA tools to accelerate the RTL lifecycle.

Drive continuous improvement in methodology, tracking metrics, and documentation.

Verification Support & Debug

Root-cause complex architectural bugs using Verdi and waveform analysis tools.

Partner with Design Verification (DV) teams to review test plans and define coverage metrics.

Support post-silicon bring-up and debug lab-failures via simulation environments.

Required Skills & Qualifications

Education: Bachelors or Master’s degree in Electrical/Electronic Engineering or Computer Engineering.

PCIe Expertise: Deep understanding of the PCIe protocol stack (Transaction, Data Link, and Physical layers).

Tools: Expert proficiency with static tools like SpyGlass, Meridian CDC, or Verdi.

Automation: Strong scripting capabilities in Python, Tcl, or Perl.

AI Exposure: Practical experience or strong knowledge of applying AI/LLM-assisted tools in hardware development.

Soft Skills: Exceptional debug capabilities, clear communication, and a highly collaborative mindset.