Senior Rtl Design Lead
Chipsilica Llp · Bengaluru · onsite · Posted 38d ago
₹36.0L - ₹72.0L PA7–12 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Responsibilities:
* Work along IP teams and integrate high speed interface IPs (PCIe Gen 6/7)
* Customize and add logic to the existing flow as per customer requirements
* Manage project timelines and resources
Perks and benefits
Annual bonus, Provident fund, House rent allowance, Employee state insurance, GratuitySourced from naukri
Skills
DdrhandsonPCIESoC IntegrationUALink