Senior RTL Design Engineer

Responsibilities:

• Design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL.
• Develop micro-architecture specifications.
• Perform RTL simulations and debug logic issues to root cause.
• Collaborate with verification engineers to develop and review test plans and coverage.

Requirements:

• Solid experience in RTL coding using Verilog/SystemVerilog.