Senior Principal System Architect(Rack level)

Key Responsibilities:

1. System Topology Architecture

• Chassis Rack Definition: Lead the structural, electrical, and logical design of the UALink switch chassis, defining high-speed backplane topologies, cabled scale-up fabrics, and multi-tier switch hierarchies.
• Signal Power Integrity Collaboration: Partner with electrical and SI/PI engineering teams to define parameters for ultra-high-speed SerDes routing across PCBs, flyover cables, and optical components, minimizing bit error rates (BER).
• Scale-Up Fabric Optimization: Architect rack-level and row-level topologies that optimize collective communication paths (e. g. , All-Reduce, All-to-All) for tens of thousands of interconnected GPUs.

2. Platform Management Software Infrastructure

• Control Plane BMC Architecture: Architect the end-to-end system management plane. Define how Baseboard Management Controllers (BMCs) monitor, configure, and provision the switch using OpenBMC, Redfish, and PLDM over MCTP.
• Boot Initialization Flows: Establish platform-level boot sequencing, multi-rail power sequencing, and secure multi-node firmware update orchestration.
• Platform Security Architecture: Define the hardware security lifecycle, including Platform Firmware Resiliency (NIST SP 800-193), secure enclave integration, and Component Attestation (SPDM).

3. Advanced RAS Infrastructure Integration

• Platform-Level RAS: Architect system-level Reliability, Availability, and Serviceability (RAS) strategies. Define how the platform isolates hardware faults, routes around failed links, handles hot-swapping of fans, power supplies, and switch blades without dropping the AI training cluster.
• Thermal Power Orchestration: Establish dynamic power management and telemetry frameworks to balance the massive transient power draws of next-generation AI workloads against rack-level cooling limits. Qualifications