Senior Physical Design Engineer

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We are seeking a highly motivated Physical Design Engineer to join our VLSI design team. The ideal candidate will be responsible for implementing and optimizing ASIC/SoC physical design flows from netlist to GDSII, ensuring timing, power, area, and signal integrity goals are achieved.

Key Responsibilities

• Perform end-to-end physical design activities including:
• Floorplanning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Physical Verification
• Timing Closure
• Analyze and fix setup/hold violations.
• Perform congestion analysis and optimization.
• Drive power, performance, and area (PPA) improvements.
• Execute Static Timing Analysis (STA) and timing signoff.
• Work on IR drop, electromigration (EM), and signal integrity checks.
• Collaborate with RTL, DFT, Verification, and Design teams for design closure.
• Support physical verification activities including DRC, LVS, and ERC.
• Develop and maintain automation scripts using TCL, Perl, Python, or Shell.
• Debug and resolve implementation issues to meet tape-out schedules