Senior Physical Design Engineer (3nm) (BB812FI RM 4548)
Sourceright Technologies · Bengaluru · onsite · Posted today
Undisclosed8–12 yrsfulltimeSourced from
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About this role
Position: Senior Physical Design Engineer (3nm) (BB812FI RM 4548)
Key skills: Block-level PnR from floorplan to GDSII, multi-GHz timing closure, CTS, OCV/POCV, SI, IR/EM, DRC/LVS, ECO, and metal-fill.
Tools required: Synopsys Fusion Compiler/ICC2 or Cadence Innovus, PrimeTime, StarRC/Quantus, Calibre, RedHawk/Voltus, TCL, and Python.
Must have hands-on 3nm (TSMC N3E/N3P or equivalent) full-block implementation through tape-out; clock-only, CAD-only, or ECO-only profiles will not be considered.
Preferred exposure: High-speed networking, AI accelerator, SerDes-adjacent silicon, UPF/low-power closure, hierarchical flows, and subsystem/top-level integration.
Role overview
Hiring Senior Physical Design Engineers to take the largest, most macro-dense, high-frequency blocks and subsystems from netlist to GDSII at 3nm. This PD engineer will own block-level closure end to end and work daily with RTL, architecture, DFT, CAD and package teams.
Hiring Senior Physical Design Engineers to take the largest, most macro-dense, high-frequency blocks and subsystems from netlist to GDSII at 3nm. This PD engineer will own block-level closure end to end and work daily with RTL, architecture, DFT, CAD and package teams.
Key responsibilities
- Own block-level PnR from floorplan to GDSII on multi-million-instance, macro-dense 3nm partitions.
- Define floorplans, macro placement, power grid and pin/feedthrough strategy that make congestion and timing converge early.
- Close multi-GHz timing: CTS (useful skew, multi-source or mesh where needed), OCV/POCV, SI and post-route optimization.
- Drive signoff: IR/EM, DRC/LVS, antenna, ECO and metal-fill to tape-out.
- Build TCL/Python automation and flow improvements that raise QoR and cut turnaround.
- Partner with architecture, RTL, DFT and CAD on partitioning, constraints and PPA trade-offs; report status and risks.
Required qualifications
- 8-12 years of physical design experience (7 minimum); BE/BTech or MS in Electrical or Electronics Engineering.
- Hands-on 3nm (TSMC N3E/N3P or equivalent) block-level implementation through tape-out. Clock-only, CAD-only or ECO-only roles do not count.
- Full-flow ownership of large, macro-dense blocks that meet the scale and frequency bar below.
- Strong in Synopsys Fusion Compiler or ICC2, or Cadence Innovus; PrimeTime, StarRC or Quantus; Calibre; RedHawk or Voltus.
- Fluent in TCL and Python (Perl or Shell is a plus); able to debug flow and QoR issues from logs.
Preferred qualifications
- Subsystem or top-level integration, hierarchical flows and partition budgeting.
- Experience on high-speed networking, AI accelerator or SerDes-adjacent silicon.
- Multi-voltage (UPF) implementation and low-power closure at 3nm.
- 2nm exposure, or technical lead experience mentoring 3+ engineers.
Job Category: Automotive EDA tools
Job Type: Full Time
Job Location: Bangalore
Experience: 8-12 Years
Notice period: immediate joiners
This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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Skills
AutomationPrimetimeCadenceeda toolsphysical designlvsfloorplanInnovuscompilerAutomotivePerlCADDFTElectronics EngineeringComputer NetworksPython AutomationEvent DrivenHigh-speed networkingDebugPythonArchitectureBudgetingArtificial Intelligence