Senior NPU Compilers Engineer

We're looking for a Senior NPU Compiler Engineer to build the compiler stack largely from the ground up that takes models from TFLite, ONNX, and PyTorch and turns them into instructions our NPU can execute.

Responsibilities:

• Design and build the full compilation pipeline: graph import, operator lowering, scheduling, memory planning, and instruction generation.
• Map neural network graphs onto a novel dataflow / Processing-in-Memory architecture.
• Optimise for execution efficiency, memory bandwidth, and power.
• Build validation tools to compare compiler output against simulator and RTL results.
• Work directly with architecture, RTL, firmware, and ML teams to shape the hardware/software interface.

Requirements:

• Strong experience building compilers, graph compilers, or backend toolchains.
• Solid C++ and Python skills.
• Deep understanding of compiler fundamentals: IRs, graph transforms, lowering, scheduling, codegen.
• Experience with ML model formats (ONNX, TFLite, PyTorch) and neural network operators/tensors.
• Background building software for NPUs, DSPs, GPUs, or other specialised accelerators.

Nice to have:

• Experience with MLIR, LLVM, TVM, XLA, Glow, or IREE.
• Familiarity with dataflow or Processing-in-Memory architectures.
• Experience with binary instruction streams, DMA engines, or on-chip SRAM.