Senior Memory Layout Engineer

Senior Memory Layout Engineer

Location: Bengaluru, India

Experience: 5–10 Years

Role Overview

We are looking for a Senior Memory Layout Engineer with strong expertise in SRAM memory layout design, advanced FinFET technology nodes, and custom layout development. The ideal candidate will have hands-on experience in memory layout implementation at 2nm, 3nm, and 5nm technology nodes, with a strong understanding of advanced-node design rules, layout optimization, and physical verification.

Key Responsibilities

• Develop and optimize custom SRAM memory layouts for advanced FinFET technology nodes.
• Execute memory layout implementation for 2nm, 3nm, and 5nm process technologies.
• Perform layout design, verification, and optimization in accordance with foundry-specific design rules.
• Work on bitcells, memory arrays, peripheral circuits, and associated layout structures.
• Perform DRC, LVS, ERC, and physical verification to ensure layout quality and manufacturability.
• Collaborate with circuit design, memory design, characterization, and physical verification teams.
• Resolve complex layout issues related to design-rule restrictions, parasitics, matching, and area optimization.
• Support layout reviews, sign-off, and design closure activities.

Required Skills

• 5–10 years of hands-on experience in custom layout design within the semiconductor industry.
• Strong expertise in SRAM memory layout and memory array implementation.
• Experience with advanced FinFET technology nodes, preferably 2nm, 3nm, and 5nm.
• Proficiency in custom layout and physical verification methodologies.
• Hands-on experience with industry-standard EDA tools such as Cadence Virtuoso and Calibre or equivalent.
• Strong understanding of DRC, LVS, parasitic extraction, design-rule constraints, and layout optimization.
• Good knowledge of CMOS device structures, matching, and parasitic effects in advanced process technologies.
• Strong debugging, problem-solving, and cross-functional collaboration skills.

Preferred Qualifications

• Experience with high-density SRAM bitcells and memory peripheral circuits.
• Exposure to foundry-specific advanced-node layout rules and FinFET design constraints.
• Experience in memory layout sign-off and silicon-proven layout methodologies.
• Understanding of layout-dependent effects and advanced-node manufacturability requirements.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.