Senior Manager - SOC Verification

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Job Description:

Job Description -

you will be a senior member in our dsPIC Microcontroller Business Unit, responsible for ensuring the functional integrity of our next-generation 32-bit MCU products. You execute complex verification strategies for SoCs featuring ARM and specialized proprietary cores.

Key responsibilities -

Participate in a global team setting on the development of advanced microcontroller products

Perform design verification of complex digital macros at the SOC level, working from an architectural description

Develop an effective suite of tests and testbench environment using VMM/UVM/System Verilog based verification

Perform RTL, Gate level verification of 16-bit Microcontroller products

Analyze gate level simulations and timing violation and work with STA team to get it resolved.

Develop Functional safety tests, fault injection simulations & coverage analysis

Debug complex issues at full chip level.

Exposure to the analog mixed signal simulations will be added plus.

Mentor junior team members

develop adoption of advanced techniques and automation.

Requirements/Qualifications:

• Education:Bachelor of Engineering in Electronics/Electrical or Computer Science, with strong digital design fundamentals.
• Experience:10+ years in SoC Verification.
• Domain Expertise: UVM, System Verilog, STA.
• Microcontrollers. Deep understanding of MCU peripherals (DMA, Timers, ADC/DAC interfaces, Security modules, Functional Safety).
• Processor Knowledge:Direct experience verifying SoCs withARM cores(Cortex-M) and proprietary RISC-based architectures.
• Methodologies:
  • Expert-level command ofSystemVerilog and UVM(Universal Verification Methodology).
  • Strong hands-on experience withFormal Verification(Property Checking, Connectivity Checking) using tools like JasperGold or VC Formal.
• Protocol Proficiency:In-depth knowledge of AMBA bus protocols (AHB, APB, AXI).
• Verification Infrastructure:Experience defining coverage-driven verification (CDV) metrics and managing massive regression suites. Module level verification plan development, TB plan, TB development and fullchip integration of the module level TB, develop effective functional assertions and coverpoints.

Preferred Skills

• Strong background in Gate-Level Simulations (GLS) and power-aware verification.
• Experience with Post-Silicon Validation, customer support and its alignment with pre-silicon test plans.
• Experience with analog mixed-mode (AMS) simulations.
• Familiarity with functional safety standards (ISO 26262) for automotive MCU applications.