Senior/Lead SoC Emulation Engineer

Senior Emulation Engineer - VELOCE / ZEBU / Palladium (Automotive SoC)

NXP is looking for a STAFFlevel Emulation Engineer with 5-10 years of handson experience in SoC emulation to work on cuttingedge automotive MCUs/SoCs. This role focuses on leading presilicon validation and software execution on industryleading emulation platforms for advanced, lowpower automotive designs.

Key Responsibilities

• Lead SoClevel emulation bringup, execution, and debug on
  Mentor/Siemens VELOCE, Synopsys ZEBU, and Cadence Palladium
• Own emulation build creation, configuration, partitioning, and optimization for complex automotive SoCs
• Enable and debug presilicon software flows using JTAG / SWD interfaces and LTB or any other debuggers
• Execute applicationspecific automotive use cases including boot flows, peripherals, power modes, and safety scenarios on emulation builds
• Drive lowpower validation and debug, including powerup/powerdown sequences
• Debug and validate clock and reset architectures, including clock trees, clock gating, reset sequencing, and crossdomain interactions
• Enable and debug multicore ARM boot flows, including primary/secondary core bringup, synchronization, and handoff sequences
• Collaborate closely with RTL, SoC verification, firmware, system, and IP teams
• Provide technical leadership and mentoring across emulation activities and methodologies

Required Skills & Experience

• 3-6 years of experience in SoC Emulation, with strong handson exposure to
  Synopsys ZEBU, Mentor/Siemens VELOCE, and/or Cadence Palladium
• Proven expertise in emulation build generation, bringup, and execution
• Strong debugging skills using JTAG / SWD and LTB debuggers
• Handson experience working on ARMbased automotive SoCs, including
  CortexM7, CortexM4, CortexM0+, and CortexR52 cores
• Solid understanding of clocking and reset architectures, including reset dependency modeling and clock domain interactions
• Strong knowledge of multicore ARM booting concepts, core enablement, reset vectors, and intercore coordination
• Solid understanding of lowpower SoC/MCU architectures, power states, clocks, and resets
• Ability to execute and debug realistic software and application workloads on emulation
• SoC Verification experience (UVM / simulation / regression debug) is a strong plus

#LI-onsite