Senior IP RTL design

Roles and Responsibilities :

• Design complex digital circuits using Verilog, ASIC, and AIX tools for various applications.
• Develop and maintain IP blocks for SoC designs, ensuring compliance with industry standards and customer requirements.
• Collaborate with cross-functional teams to integrate IP blocks into larger system-on-chip (SoC) designs.
• Troubleshoot issues related to RTL code quality, timing closure, and area optimization.

Job Requirements :

• 5-15 years of experience in ASIC design engineering with expertise in Verilog, ASIC, AIX, CDC, CDEC, LINT, RDC.
• Strong understanding of RTL coding best practices and ability to write high-quality code quickly.
• Experience working on multiple projects simultaneously while meeting tight deadlines.