Senior Engineer - Physical Design
MosChip Technologies · Hyderabad · onsite · Posted 22d ago
Undisclosed3–8 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Responsibilities
- block level / top-level floor planning
- PG Planning
- partitioning (for hierarchical designs)
- placement
- scan-chain-reordering
- clock tree synthesis
- timing optimization
- SI aware routing
- timing analysis/closure and ECO tasks (timing and functional ECOs)
- SI closure
- design rule checks (DRC)
- Logical vs. Schematic (LVS) checks
- Antenna checks
- be able to fix the violations
- Provide technical guidance, mentoring to physical design engineers
- Interface with front-end ASIC teams to resolve issues
- Excellent communication skills
- Strong background of ASIC Physical Design: Floor planning, PR, extraction, IR Drop Analysis, Timing and Signal Integrity closure
- Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools
- Expertise in scripting languages such as PERL, TCL
- Strong Physical Verification skill set
- Static Timing Analysis in PrimeTime or PrimeTime-SI
- Good written and oral communication skills. Ability to clearly document plans
- Ability to interface with different teams and prioritize work based on project needs
- Experience 3 to 8 Years
- Location: Hyderabad
Sourced from naukri
Skills
ScriptingStatic Timing AnalysisPrimetimeSignal IntegrityCadencephysical designlvsfloor planningsynthesisscripting languagesPerlASICsynopsysClock Tree SynthesisNode.JsCommunication SkillsPhysical Verification
About MosChip Technologies
MosChip Technologies
Semiconductors
1.4k+
employees
1999
27 years old
Hyderabad/Secunderabad, Telangana
India
₹11.6L PA avg
Avg at MosChip Technologies
About
Established in 1999, MosChip is the First Fabless Semiconductor company publicly traded in India with 20+ years of experience focused on Embedded Systems, System Engineering, and IoT Solutions.
Industries
SemiconductorsEmerging Technologies
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