Senior Engineer - IC Design

Job Summary

Senior Engineer to join Silicon Engineering Team in Hyderabad. In this role, you will drive the design, implementation, and optimization of advanced SoCs using state-of-the-art physical design methodologies in low power. You will be a domain expert in Physical Verification and EM/IR drop analysis and fixing. You will collaborate with PD leads and FP/PnR engineers across multiple SOCs to fix Floorplan PG Grid issues. Ensure Signal/Power Integrity and run Static/Dynamic IR analysis using industry-standard tools. Own Physical Verification from FP to PG while mentoring junior engineers and collaborating with cross-functional groups. This is an excellent opportunity to contribute to world-class silicon solutions and grow as a technical leader.

Responsibilities

• Lead and execute the end-to-end low power physical verification flow including but not limited to DRC, LVS, PERC resistance checks for complex SoCs and IP blocks (RTL handoff to GDSII).
• Understand the Analog/Backplane IP Integration guidelines to ensure compliance.
• Run power analysis and define/drive strategies for signal power EM analysis to be deployed across multiple SoCs.
• Run static/dynamic IR analysis at various stages of designs and provide feedback.
• Debug grid weakness/RCA and provide solutions to meet stringent IR drop targets.
• Collaborate with Floorplan, PnR and IO ring responsibilities and packaging teams for seamless integration and alignments.
• Responsible for GDS streamout, versioning check, PG fill insertion, density checks and PG.
• Drive EDA tool automation and methodology improvements for efficiency and scalability.
• Be a domain SPOC and mentor; guide junior members to foster technical growth.
• Work with foundries and vendors on process bring-up, PDK updates, and tape-out readiness.

Requirements

• Bachelor's/Master's degree in ECE, EEE or related fields.
• 4+ years of experience in ASIC physical design with focus on PV/Power/EM/IR drop analysis.
• Strong hands-on expertise in industry-standard tools such as Cadence Innovus, Voltus, Pegasus, Mentor Calibre, etc.
• Deep understanding of the architecture-to-GDSII flow and sign-off requirements.
• Excellent problem-solving, leadership, and communication skills.

Preferred Qualifications

• Experience in chip-level integration and hierarchical design methodologies.
• Familiarity with place route and Static Timing Analysis (IRSTA, etc.).
• Knowledge of UPF/CPF, power gating, DVFS, and other low-power techniques.
• Previous experience with cross-site collaboration.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.