Senior Engineer IC Design (Physical Design - PV/Power/EM/IR Drop Engineer)

Meet the team:

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry's toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that's one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance.

About the role:

We are seeking a highly skilled Senior Engineer to join our Silicon Engineering Team in Hyderabad. In this role, you will drive the design, implementation, and optimization of advanced SoCs using state-of-the-art physical design methodologies in low power. You will be a domain expert in area of Physical Verification and EM/IR drop analysis and fixing. You will work with close collaboration with PD leads and FP/PnR engineers across multiple SOCs to fix Floorplan & PG Grid issues. Ensure Signal/Power Integrity and run Static/Dynamic IR analysis using Industry standard tools, Own Physical Verification starting from FP till PG while mentoring junior members of engineers and collaborating with cross-functional groups. This is an excellent opportunity to contribute to world-class silicon solutions and grow as a technical leader.

Responsibilities:

• Lead and execute the end-to-end low power & physical verification flow including but not limited to DRC, LVS , PERC & resistance checks for complex SoCs and IP blocks (RTL handoff to GDSII).
• Understand the Analog / Backplane IP Integration guidelines & ensure compliance.
• Run power analysis and Define/drive strategies for Signal & Power EM analysis to be deployed across multiple SoCs.
• Run Static & Dynamic IR analysis at various stages of designs and provide feedback.
• Debug grid weakness/RCA and provide solutions to meet stringent IR drop targets.
• Collaborate with Floorplan, PnR and IO ring responsible and packaging teams for seamless integration and alignments.
• Responsible for GDS streamout, versioning check, PG fill insertion, density checks and PG.
• Drive EDA tool automation and methodology improvements for efficiency and scalability.
• Be a domain SPOC and mentor, guide junior members to foster technical growth.
• Work with foundries and vendors on process bring-up, PDK updates, and tape-out readiness.

Requirements:

• Bachelor's/Master's degree in ECE, EEE or related fields.
• 4+ years of experience in ASIC physical design with focus on PV/Power/EM/IR drop analysis
• Strong hands-on expertise in Industry standard tools like – Cadence Innovus, Voltus , Pegasus, Mentor-Calibre etc
• Deep understanding of the architecture-to-GDSII flow and sign-off requirements.
• Excellent problem-solving, leadership, and communication skills.

Preferred Qualification:

• Experience in chip-level integration and hierarchical design methodologies.
• Familiarity with Place & route and Static Timing Analysis (IRSTA etc) .
• Knowledge of UPF/CPF, power gating, DVFS, and other low-power techniques.
• Previous experience with cross-site collaboration.

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Equity Rewards (RSUs)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support