Senior Engineer - Design Verification

3. DV:

Key Responsibilities

IP Verification

• Develop comprehensive verification plans based on design specifications and architecture documents.
• Verify complex Digital IPs and Subsystems at block and subsystem levels.
• Create reusable and scalable verification environments using UVM methodology.
• Develop test plans, test cases, checkers, scoreboards, assertions, and coverage models.
• Ensure thorough functional coverage and closure.

Testbench Development

• Develop UVM-based verification components including:
  • Drivers
  • Monitors
  • Agents
  • Sequencers
  • Scoreboards
  • Reference Models
• Create constrained-random and directed test scenarios.
• Improve verification productivity through reusable VIPs and automation.

Protocol Verification

• Verify industry-standard protocols such as:
  • PCIe Gen4/Gen5/Gen6
  • DDR4/DDR5
  • LPDDR4/LPDDR5
  • USB 2.0/3.x
  • Ethernet
  • MIPI CSI/DSI
  • AXI/AHB/APB
  • UCIe
  • CXL
  • NoC & Interconnect Protocols

Debug & Analysis

• Debug simulation failures and identify RTL issues.
• Analyze waveform dumps and protocol transactions.
• Collaborate with RTL, Architecture, Physical Design, DFT, and Firmware teams to resolve functional bugs.
• Support pre-silicon verification and post-silicon validation activities.

Coverage Closure

• Drive:
  • Functional Coverage
  • Code Coverage
  • Assertion Coverage
  • Branch Coverage
  • Toggle Coverage
• Analyze coverage gaps and develop closure strategies.

Formal Verification (Preferred)

• Develop and execute formal verification plans.
• Create SystemVerilog Assertions (SVA).
• Verify protocol compliance and critical design properties using formal tools.

Required Technical Skills

Verification Methodologies

• SystemVerilog
• UVM (Universal Verification Methodology)
• OVM/VMM (Good to Have)
• Assertions (SVA)
• Coverage-Driven Verification
• Constrained Random Verification

Verification Expertise

Strong experience in:

IP Verification

Subsystem Verification

Functional Verification

Verification Planning

Coverage Closure

Debugging & Root Cause Analysis

Assertion-Based Verification

Regression Management

Verification Signoff

Protocol Experience (One or More Preferred)

• PCIe
• DDR4 / DDR5
• LPDDR4 / LPDDR5
• USB
• Ethernet
• MIPI CSI/DSI
• UFS
• SATA
• AXI
• AHB
• APB
• CXL
• UCIe
• NoC
• RISC-V Subsystems

EDA Tool Experience

Synopsys

• VCS
• Verdi

Cadence

• Xcelium
• SimVision
• JasperGold (Preferred)

Siemens/Mentor

• QuestaSim
• Questa Formal

Programming & Scripting

Strong knowledge of:

• SystemVerilog
• Verilog
• Python
• Perl
• Tcl
• Shell Scripting

Preferred Qualifications

Advanced Verification Skills

• Formal Verification
• Low Power Verification (UPF/CPF)
• CDC/RDC Verification
• Emulation and FPGA Prototyping
• AI/ML Accelerator Verification
• SoC Verification

Domain Experience

Experience in one or more of the following:

• Networking SoCs
• Datacenter Products
• CPU Verification
• GPU Verification
• AI/ML Accelerators
• Automotive SoCs
• Wireless Communication
• Storage Controllers
• Consumer Electronics

Educational Qualification

• B.E. / B.Tech / M.E. / M.Tech in:
  • Electronics & Communication Engineering
  • Electrical Engineering
  • VLSI Design
  • Microelectronics
  • Computer Engineering

Roles and Responsibilities
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.