Senior EMIR Physical Design Engineer-HYDERABAD

Company Description:

MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with a team of 2500+ engineers across Silicon Valley, USA, and India. The company delivers end-to-end services spanning silicon design, verification, systems, software, and device engineering, along with multimedia, mobility, connectivity, AI/ML solution design, and test automation. MosChip® also focuses on Digital IPs, Verification IPs, Mixed Signal IPs development, and Turnkey ASIC services for global clients. The organization has shipped millions of connectivity ICs and achieved an excellent record of first-time-right silicon in over 200 SoC tape-outs, offering engineers exposure to complex, high-impact projects. Team members benefit from working in a technology-driven environment with opportunities to contribute to cutting-edge semiconductor solutions.

Role Description:

The Senior EMIR Physical Design Engineer – Hyderabad is a full-time, on-site role responsible for driving EMIR (Electromigration and IR drop) analysis and closure across complex SoC designs. This position involves performing physical design tasks such as floorplanning, placement, clock tree synthesis, routing, and timing closure, with a strong focus on power integrity and reliability. The engineer will collaborate with logic, RTL, and circuit design teams to implement robust design methodologies, validate EMIR constraints, and ensure sign-off quality through physical verification. Day-to-day activities include running industry-standard EDA tools, debugging EMIR issues, optimizing power grid and layout, preparing reports and documentation, and supporting tape-out schedules. The role also requires mentoring junior engineers, participating in design reviews, and contributing to continuous improvement of physical design flows and best practices.

Required Experience:

• 5+ years of overall VLSI/Physical Design experience is preferred.
• 3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.
• Strong expertise with industry-standard EMIR analysis and sign-off methodologies.
• Excellent debugging, analytical, and cross-functional collaboration skills.

Key Responsibilities:

• Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
• Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
• Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
• Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
• Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
• Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.