{"@context":"https://schema.org","@type":"JobPosting","title":"Senior DV Engineer","description":"

Key Responsibilities:

Develop and execute verification plans for high-speed interface IPs including PCIe, DDR, USB, UCIe, Ethernet, and CXL.
Build and maintain SystemVerilog/UVM-based verification environments.
Develop testcases, assertions (SVA), functional coverage, and scoreboards.
Perform protocol compliance, regression, and debug activities.
Collaborate with design, architecture, and validation teams to ensure quality IP delivery.

Required Skills:

Strong expertise in SystemVerilog, UVM, and assertion-based verification.
Experience verifying one or more protocols: PCIe, DDR, USB, UCIe, Ethernet, or CXL.
Knowledge of verification methodologies, functional coverage, and debugging.
Familiarity with EDA simulators and scripting (Python/Perl/Shell) is an added advantage.
Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related field.

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