BENGALURU · FULLTIME
Senior DV Engineer
BITSILICA
Bengaluru · onsite · Posted 9d ago
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Not disclosed4–6 yrsfulltimeBengaluru
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Section · 01
About this role
Bitsilica is hiring a Senior Design Verification Engineer with strong hands-on experience in SystemVerilog and UVM.
Experience: 4+ years of relevant experience in Design Verification
Key Skills:
- Strong hands-on experience in SystemVerilog
- Strong expertise in UVM methodology
- Good understanding of Design Verification concepts and methodologies
- Experience in developing UVM testbenches, test cases, sequences, drivers, monitors, scoreboards, and functional coverage
- Good debugging and problem-solving skills
- Experience with simulation, regression, coverage analysis, and bug tracking
- Ability to understand specifications and develop verification plans and environments
Good to Have
Recent hands-on experience with any of the following protocols is an added advantage:
- PCIe
- Ethernet
- DDR
- CXL
- Other high-speed or industry-standard protocols
Location: Bangalore / Hyderabad
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Section · 02
Skills
Test CasesDesign Verification concepts and methodologiessimulation regression coverage analysisMonitorsbug trackingUVMSystem VerilogdriversUVM testbenchesFunctional Coveragescoreboardsverification planssequences