Senior Design Verification Engineer

Responsibilities

• Develop test plans and verification strategies for IP and SoC designs.
• Build and maintain UVM-based testbenches.
• Develop directed and random test cases to verify functionality and corner cases.
• Debug simulation failures and resolve design issues with engineering teams.
• Verify protocols such as DDR, PCIe, or Ethernet.
• Achieve code and functional coverage closure.
• Collaborate with RTL, design, validation, and software teams.
• Automate testing and regression using Python, Perl, or shell scripting.

Requirements

• Hands-on design verification experience.
• Expertise in at least one protocol: DDR, PCIe, or Ethernet.
• Proficiency in Verilog, SystemVerilog, and UVM.
• Strong digital design and verification fundamentals.
• Experience with industry-standard simulators and debugging.