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    Job · 22086742

    Interex semiconductor logo

    Senior Design Verification Engineer

    Interex semiconductor · Bengaluru · onsite · Posted 6d ago

    Not disclosedFresherfulltimeSourced fromFoundit

    About a minute. You'll make an account on the way through.

    About this role

    Company Description Interex Semiconductor provides custom ASICs, Silicon IPs, advanced solutions, and specialized services for a wide range of technology applications. The company focuses on helping clients build differentiated semiconductor products that meet demanding performance and efficiency requirements. By combining deep domain expertise with flexible engagement models, Interex Semiconductor supports customers from concept through production. As the semiconductor landscape evolves, the organization remains committed to innovation, quality, and long-term partnerships that enable client success.

    Role Description This is a full-time, on-site Senior Design Verification Engineer role based in Bengaluru. The Senior Design Verification Engineer will lead verification planning, testbench architecture, and execution for complex ASIC and IP designs, collaborating closely with RTL and architecture teams. Typical responsibilities include creating verification plans, developing and maintaining testbenches and constrained-random test scenarios, writing assertions, and performing coverage analysis to ensure design quality. The role also involves systematic debugging of functional issues, root-cause analysis, and driving closure on verification gaps, while mentoring junior engineers and contributing to process and methodology improvements.

    Qualifications

    • Strong Functional Verification and Debugging skills, including experience with testbench development, simulation environments, and coverage-driven verification.
    • Solid RTL Design and Computer Architecture knowledge, with the ability to understand micro-architectural specifications and translate them into effective verification strategies.
    • Hands-on experience in Formal Verification methodologies and tools, including assertion-based verification and property checking.
    • Proficiency with industry-standard EDA tools and languages (e.g., SystemVerilog, UVM, simulation and formal tools from major vendors).
    • Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field, with several years of relevant design verification experience.
    • Strong analytical and problem-solving abilities, effective communication skills, and a collaborative approach to working with cross-functional engineering teams.
    • Experience in ASIC/IP development flows, version control, and scripting (e.g., Python, Perl, or Shell) is highly beneficial.

    Sourced from foundit

    Skills

    formal verificationeda toolscomputer architectureshellTestbench DevelopmentPerlUVMSystem VerilogRTL DesignFunctional VerificationCoverage-Driven VerificationAssertion-based verificationdebuggingPythonProperty Checkingsimulation environments

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