BENGALURU · FULLTIME
Senior Design Verification Engineer

Allegis Group
Bengaluru · onsite · Posted 12d ago
Your match
Sign in to see your match score, skill gaps & tailored resume.
Section · 01
About this role
Hiring: Senior Design Verification Engineer | Bangalore | 5-12 Years
We are looking for an experienced Senior Design Verification Engineer to join Product company a high-performance verification team working on advanced IP/SoC verification projects.
Mandatory Skills
SystemVerilog & UVM with strong IP Verification experience
AXI Protocol Verification (AXI4/AXI4-Lite/AXI-Stream)
Regression Triaging & Root Cause Analysis
Functional Coverage, Assertions, Scoreboards, Checkers
RTL Debug, Waveform Analysis, Verification Sign-off
Good to Have
PCIe Gen3/Gen4/Gen5 Verification
Experience with AI tools such as Copilot, ChatGPT, Claude, Gemini
Verification Automation & Prompt Engineering
Key Responsibilities
- Develop reusable UVM-based verification environments.
- Create directed and constrained-random test scenarios.
- Drive code, functional, assertion, and toggle coverage closure.
- Perform regression triaging and debug complex failures.
- Verify AXI and PCIe-based IPs/subsystems.
- Collaborate closely with Design, Firmware, and Architecture teams.
- Utilize AI-driven solutions to improve verification productivity and debug efficiency.
Experience
5-12 Years
Location
Bangalore
Notice Period
Immediate to 30 Days Preferred
Sourced from naukri
Let the agent run this one for you.
Tailored resume, auto-apply, and referral lookup — in under 2 minutes.
Section · 02
Skills
Section · Company
About Allegis Group

Allegis Group
Recruitment
913
employees
1983
43 years old
Hanover, Maryland
United States (USA)
About
Industries
Employee ratings
448 reviews
Culture
3.5
Career growth
2.8
Work-life
3.6
Employees rate it well for
Find them on