Senior Design Verification Engineer
Einfochips · Hyderabad · onsite · Posted 23d ago
Undisclosed4–8 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
- 4 - 8 years of experience in ASIC/SoC/IP Design Verification.
- Strong hands-on expertise in SystemVerilog and UVM.
- Good understanding of Ethernet MAC architecture and functionality.
- Good understanding of Ethernet PHY / PCS (Physical Coding Sublayer).
- Familiarity with Ethernet standards and concepts such as MAC/PCS datapath, packet framing, encoding/decoding, link establishment, and error handling.
- Strong experience in developing UVM testbenches, sequences, drivers, monitors, scoreboards, and functional coverage.
- Good understanding of constrained-random verification and coverage-driven verification.
- Experience with debugging simulation failures and waveform analysis.
- Good knowledge of RTL design concepts, digital logic, and common on-chip interfaces.
- Experience with coverage analysis and closure, including functional and code coverage.
- Good scripting/debugging skills using Python, Perl, Tcl, or similar is a plus.
Sourced from naukri
Skills
verificationEthernetASIC VerificationUVMSystem VerilogIp VerificationSOC VerificationDesign Verification
About Einfochips
Einfochips
IT Services & Consulting
3.2k+
employees
1994
32 years old
San Jose, California
United States (USA)
About
eInfochips, an Arrow company, is a product engineering and semiconductor design services firm, specializing in digital transformation and connected IoT solutions across various cloud platforms.
Industries
IT Services & ConsultingDesignEngineering & Construction
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