Senior Design Verification Engineer

Senior Design Verification Engineer – SoC / Ethernet

Location: Bengaluru

Experience: 6–10 Years

Role Overview

We are seeking a Senior Design Verification Engineer with strong hands-on expertise in SoC verification and Ethernet protocols. The role involves developing scalable verification environments, validating complex SoC IPs, and driving functional correctness through advanced SystemVerilog and UVM methodologies.

Key Responsibilities

• Develop and execute comprehensive SoC verification strategies for Ethernet IPs and complex subsystems.
• Build scalable, reusable SystemVerilog/UVM testbenches, including agents, scoreboards, monitors, and coverage models.
• Verify Ethernet protocols, data paths, packet processing, and corner-case scenarios.
• Develop constrained-random, directed, and assertion-based tests for functional validation.
• Drive functional coverage closure, regression stability, and root-cause analysis of RTL failures.
• Collaborate with RTL, architecture, emulation, and system teams to deliver high-quality SoC designs.

Core Technical Requirements

• 6–10 years of hands-on experience in SoC / IP Design Verification.
• Strong expertise in SystemVerilog and UVM.
• Solid experience in Ethernet verification, including packet-level validation and protocol behavior.
• Understanding of Ethernet standards such as 10G / 25G / 40G / 100G Ethernet is preferred.
• Proficiency in testbench architecture, functional coverage, assertions, and constrained-random verification.
• Strong RTL simulation, waveform debug, and regression analysis skills.
• Experience with Python, C/C++, or scripting for verification automation is preferred.

Technical Ownership

• Own verification deliverables for critical Ethernet IPs and SoC subsystems.
• Drive coverage closure, debug complex failures, and improve verification infrastructure.
• Contribute to verification methodology, reusable components, and design quality.