Senior Design Verification Engineer

Role & responsibilities :

* Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy.
* Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies.

Core Requirements:
* Strong Communication Skills: Ability to collaborate effectively within a team.
* Leadership: Guide new team members and engineers, sharing your knowledge and experience.
* Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs.
* Proficiency in SPICE and/or Verilog simulations.

Preferred candidate profile : Required Skills:
* Experience with SystemVerilog, PLI coding, and UVM Test Benches.
* Expertise in DRAM, SRAM, or other memory-related fields.
* Familiarity with AMS verification and co-simulation is a plus.
* Experience with Ethernet, SATA, Perl Scripts, and Debugging is helpful.
* Knowledge of full-chip DDR, gate-level simulation, and SPICE simulation is optional but advantageous.

Perks and benefits : Flexible Working Hours , Transport facility, Competitive Salary