Senior Design Verification Engineer

Role & responsibilities

• 5+ years of strong experience in Design Verification using SystemVerilog and UVM methodology.
• Hands-on experience with high-speed interface protocols such as PCIe, USB, DDR, Ethernet, AXI, etc.
• Good understanding of verification concepts, functional coverage, code coverage, assertions (SVA), and debugging.
• Experience in developing and maintaining UVM-based verification environments, testbenches, sequences, drivers, monitors, and scoreboards.
• Experience with simulation and debugging tools such as VCS, Questa, Xcelium, or equivalent.
• Exposure to SoC/IP-level verification is an added advantage.