Senior Design Verification Engineer

We are looking for an experienced Senior Design Verification Engineer with 4+ years of hands-on experience in SoC/ASIC Design Verification. The ideal candidate should have strong expertise in SystemVerilog, UVM, functional coverage, assertions, and high-speed interface protocols.

Strong experience in System Verilog and UVM methodology

Hands-on expertise in high-speed interface protocols (PCIe / USB / DDR / Ethernet / AXI, etc.)

Good understanding of verification concepts, coverage, assertions, and debugging

Experience with simulation tools (VCS, Questa, Xcelium, etc.

Strong analytical & problem-solving skillsRole & responsibilities