Senior Design Verification Engineer

Roles and Responsibilities :

• Design verification of complex digital circuits using SystemVerilog, UVM, and other relevant tools.
• Collaborate with cross-functional teams to identify requirements and develop test plans for functional verification.
• Develop and execute tests to validate the functionality of PCIe, DDR, Ethernet interfaces on ASIC designs.
• Analyze results, debug issues, and provide recommendations for improvement.

Job Requirements :

• 5-15 years of experience in ASIC verification using IP Verification methodologies (UVM).
• Strong understanding of SystemVerilog programming language and its application in DDRA/IP verification.
• Protocol Expertise – Experience in PCIe, UCIe, LPDDR, ethernet or DDR related verification or design.
• Preferred: SoC Verification – Candidates with experience in verification of RISC-V or ARM-based SoC platforms.