Senior Design Verification Engineer

Job Summary

Quadric is building a revolutionary new processor-based SoC architecture. As a Senior Design Verification Engineer, you will join the ground floor of our chip design team, taking technical leadership in architecting and building our SoC-level verification environment from scratch. You will collaborate closely with architects, hardware engineers, and software teams to ensure high quality and complete verification coverage for our next-generation GPNPU-based SoCs.

Responsibilities

Testbench Architecture Test Plan Development

• Architect and build novel, scratch-built testbenches for SoC-level verification of our GPNPU-based SoCs.
• Collaborate cross-functionally with architects, HW designers, and SW teams to document comprehensive verification test plans.
• Implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities.

Test Execution Verification Coverage

• Develop directed and random drivers, as well as assembly or C++ programs, to efficiently stress-test SoC subsystems and integration.
• Verify complex SoC subsystems, including 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
• Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites.
• Track, analyze, and communicate verification progress across teams using functional and code coverage metrics.

What Success Looks Like

• Within your first 6-12 months, you'll:
• Build out and deploy a fully functional, scratch-built SoC-level UVM verification environment.
• Achieve target coverage metrics across all critical SoC subsystems and 3rd-party IP blocks.
• Establish robust co-simulation pipelines that validate HW/SW execution before tapeout.

Requirements

• Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs.
• Deep expertise in UVM methodology and leading SoC-level verification practices.
• Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python.
• Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
• Strong computer architecture background with experience in VCS and Verilog/C Co-Simulation.

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