Senior Design Verification Engineer : Bangalore

We are looking for an experienced Verification Engineer with strong expertise in SystemVerilog, UVM, and Ethernet protocol verification to join our growing semiconductor/VLSI team.

Key Responsibilities

• Develop and execute verification plans for complex digital/IP/SoC designs.
• Build scalable and reusable verification environments using SystemVerilog and UVM methodology.
• Create testbenches, test cases, assertions, checkers, and coverage models.
• Perform protocol verification with strong focus on Ethernet-based designs.
• Debug simulation failures and collaborate closely with design and architecture teams.
• Analyze functional/code coverage and ensure verification closure.
• Participate in regression execution and automation activities.
• Support bring-up and validation activities when required.

Mandatory Skills

• Strong hands-on experience in SystemVerilog (SV) and UVM
• Good understanding of Ethernet protocols
• Experience in verification environment development and debugging
• Strong knowledge of digital design and verification concepts
• Experience with simulators like VCS/Xcelium/Questa
• Understanding of assertions, coverage-driven verification, and scripting

Preferred Skills

• Experience in SoC/IP verification
• Knowledge of protocols such as AXI/APB/AHB is an added advantage
• Familiarity with Python/Perl/Shell scripting
• Strong debugging and problem-solving skills

Qualification

• Bachelors or Masters degree in Electronics/ECE/VLSI or related field

Interested Candidates

Interested can share resume on [email removed]