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    Job · 16802829

    NT

    Senior Design Verfication Engineer - UVM/System Verilog

    NobleEdge Talent Advisory · Bengaluru · onsite · Posted 84d ago

    Not disclosed7–15 yrsfulltimeSourced fromHirist

    About a minute. You'll make an account on the way through.

    About this role

    Senior Design Verfication Engineer - UVM/System Verilog

    Sourced from hirist

    Skills

    AtpgMixed SignalUVMSystem VerilogDesign VerificationDFT

    Senior Design Verfication Engineer - UVM/System Verilog · waiting for your command