Senior Analog Layout Engineer
NEWSOFT CONSULTANTS · Bengaluru · onsite · Posted 31d ago
₹35.0L - ₹80.0L PA4–9 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
UCIe/SerDes PHY block: Floorplan to signoff. Layout: TX/RX, PLL/DLL, CDR, clocking, driver, receiver high-speed I/O circuit
Block/PHYlevel floorplanning, power planning, matching, shielding signal-integrity optimization. DRC/LVS/ERC/PEX/EMIR closure.
Block/PHYlevel floorplanning, power planning, matching, shielding signal-integrity optimization. DRC/LVS/ERC/PEX/EMIR closure.
Required Candidate profile
Analog/Custom IC L/O. Analog/SerDes/PHY. Parasitics, noise isolation, shielding, differential routing. Advanced FinFET/GAA/leading-edge CMOS techs. DRC/LVS/PEX/EMIR/signoff. UCIe/PCIe/SerDes/DDR/PHYSourced from naukri
Skills
SERDES PHY BlocksdlllvsfloorplanpllEthernetDRCPCIErxcdrSerdesPHYTxEMIR