Senior Analog Layout Engineer

Company Description FermionIC Design is a fabless semiconductor company focused on high-speed SERDES and PLL technologies for next-generation interfaces. The team designs advanced multi-protocol retimers that support PCIe 5.0 and USB4, enabling reliable high-bandwidth data transmission. As a specialized, technology-driven organization, FermionIC offers opportunities to work on complex mixed-signal ICs and cutting-edge high-speed design challenges. Team members collaborate closely across design, verification, and layout to deliver robust products for demanding global markets.

Role Description This is a full-time, on-site Analog Layout role based in Bengaluru. The analog layout engineer will be responsible for creating, optimizing, and validating transistor-level layouts for high-speed SERDES, PLLs, and related analog/mixed-signal circuits. Day-to-day tasks include floorplanning, device placement, routing, matching, and parasitic minimization, as well as ensuring DRC, LVS, and reliability compliance using industry-standard EDA tools. The role involves close collaboration with circuit designers to interpret schematics, review layout for performance and robustness, and iterate on improvements. The engineer will also support tape-out activities, contribute to layout methodology enhancements, and maintain thorough documentation of layout decisions and design constraints.

Qualifications

• Candidates should possess strong skills in analog and mixed-signal Layout Design, including transistor-level layout, matching techniques, and floorplanning for high-speed SERDES/PLLs.
• Candidates should possess foundational Graphics and Page Layout skills relevant to organizing and visualizing complex layout views and documentation.
• Candidates should possess basic Graphic Design capabilities for preparing clear technical diagrams, layout illustrations, and presentation materials when needed.
• Candidates should possess familiarity with Digital Marketing concepts only as a plus, for contributing to technical content or collateral that explains layout and design capabilities.
• Proficiency with industry-standard EDA tools (e.g., Cadence Virtuoso or equivalent) and understanding of DRC, LVS, and reliability checks.
• Solid knowledge of semiconductor device physics, analog circuit fundamentals, and parasitic effects in high-speed designs.
• Strong analytical and problem-solving skills, attention to detail, and ability to work collaboratively in cross-functional teams.
• Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field, with prior experience in analog/mixed-signal IC layout preferred.