Senior Analog/Custom Layout Engineer

Position: Analog Custom Layout Engineer

Experience: 5 to 8 Years
Location: Hyderabad
Industry: Semiconductor / VLSI

Technology Node: TSMC 3nm experience is mandatory, exposure to 5nm/7nm/16nm FinFET is a plus.

Key Responsibilities:

• Design and development of critical analog, mixed-signal, custom digital blocks, and full-chip level integration.
  
• Perform layout verification (LVS, DRC, Antenna rule checks), quality checks, and documentation support.
  
• Ensure on-time delivery of block-level layouts with high quality and accuracy.
  
• Collaborate with engineering teams to assure the success of layout projects across multiple projects.
  
• Demonstrate strong problem-solving capabilities in physical verification.
  
• Mentor and guide junior team members in sub-block level layout execution and review of critical design elements.
  
• Support project management activities and milestone tracking.
  

Technical Skills:

• Layout Tools: Cadence VLE/VXL
  
• Verification Tools: Mentor Graphics Calibre (DRC/LVS)
  
• Physical Verification: DRC, LVS, Antenna checks
  
• Technology Nodes: TSMC 3nm (mandatory), 5nm, 7nm, 16nm FinFET
  
• Strong understanding of analog/custom layout techniques in advanced CMOS processes
  

Educational Qualification:

• BE/MTech in Electronics or VLSI Engineering
  
• Minimum 5 years of hands-on experience in analog/custom layout design