Semiconductor Engineer

Job Title: Senior Engineers Multiple Openings

Location: Chennai, Hyderabad, Bangalore

Experience: 4+ years of relevant experience
Work Mode: Work from Office

We are hiring experienced VLSI/ASIC engineers for multiple opportunities across front-end design, physical implementation, verification, sign-off, DFT, and memory design.

Candidates should have hands-on experience in their respective domain, strong exposure to relevant Cadence tools, and experience delivering production-quality ASIC/SoC projects.

Open Positions

1. Physical Verification (PV)

• Hands-on experience in physical verification and sign-off.
• Expertise in DRC, LVS, ERC, antenna, density, and reliability checks.
• Experience debugging complex physical verification violations.
• Cadence Pegasus or PVS experience preferred.
• Knowledge of Cadence Quantus for parasitic extraction is advantageous.
• Experience with advanced/lower technology nodes is preferred.

1. Place and Route (PnR)/Physical Design Lead

• Strong block or subsystem ownership from netlist to GDSII.
• In-depth hands-on expertise in Cadence Innovus is mandatory.
• Experience in floorplanning, power planning, placement, CTS/CCOpt, routing, optimization, and physical ECOs.
• Strong understanding of congestion, timing closure, clock skew, signal integrity, and design-rule issues.
• Experience with Cadence Tempus, Quantus, and Voltus is preferred.
• Experience in advanced technology nodes such as 7 nm, 5 nm, 4 nm, or below is highly desirable.
• Ability to lead blocks, mentor engineers, and coordinate with STA, DFT, RTL, and sign-off teams.

1. Full-Chip STA Engineer

• Strong full-chip static timing analysis and sign-off experience.
• Hands-on expertise in Cadence Tempus.
• Experience in MMMC analysis, timing constraints, clock definitions, exceptions, and timing ECOs.
• Strong knowledge of setup, hold, recovery, removal, clock-gating, and asynchronous timing checks.
• Experience with OCV, AOCV, POCV/SOCV, SI/crosstalk, and variation-aware analysis.
• Ability to debug timing violations across hierarchical and full-chip designs.
• Experience working closely with PnR teams for timing closure.

1. Synthesis and STA Engineer

• Hands-on experience in RTL synthesis and timing closure.
• Expertise in Cadence Genus and Tempus.
• Strong knowledge of SDC constraints, synthesis optimization, QoR analysis, and timing reports.
• Experience in low-power synthesis, UPF, multi-clock, and multi-voltage designs.
• Familiarity with Cadence Conformal for LEC/formal equivalence checking.
• Ability to debug synthesis, constraint, and timing issues.

1. DFT Engineer

• Experience in scan insertion, ATPG, fault simulation, and coverage closure.
• Hands-on exposure to Cadence Modus.
• Knowledge of compression, MBIST, LBIST, boundary scan/JTAG, and test-mode timing.
• Experience debugging scan-chain, pattern-generation, and simulation failures.
• Understanding of stuck-at, transition, and other fault models.
• Experience supporting silicon bring-up and yield/debug activities is advantageous.

1. Design Verification (DV) Engineer

• Strong experience in SystemVerilog and UVM-based verification.
• Hands-on experience with Cadence Xcelium and SimVision.
• Experience in testbench development, assertions, functional coverage, and coverage closure.
• Exposure to Cadence vManager and JasperGold is preferred.
• Strong debugging skills across RTL, testbench, protocol, and regression failures.
• Experience with formal verification, emulation, or SoC-level verification is advantageous.

1. Memory Design Engineer

• Experience in custom memory circuit design, simulation, and characterization.
• Hands-on knowledge of Cadence Virtuoso, Spectre, and ADE.
• Experience designing SRAM, ROM, register-file, or memory-compiler circuits.
• Strong understanding of bit cells, sense amplifiers, write drivers, decoders, control circuits, and timing paths.
• Experience in PVT and Monte Carlo analysis.
• Cadence Liberate experience for library characterization is preferred.
• Knowledge of power, performance, area, yield, and reliability optimization.

1. Memory Layout Engineer

• Experience in full-custom memory layout using Cadence Virtuoso.
• Strong understanding of layout matching, symmetry, parasitics, electromigration, and reliability requirements.
• Experience in DRC, LVS, ERC, and parasitic-extraction closure.
• Hands-on experience with Cadence Pegasus/PVS and Quantus is preferred.
• Experience with SRAM, ROM, register-file, or memory-periphery layout.
• Exposure to advanced technology nodes is preferred.

1. RTL Design Engineer

• Strong experience in Verilog/SystemVerilog RTL design.
• Experience in microarchitecture development, RTL coding, integration, and debugging.
• Knowledge of lint, CDC/RDC, synthesis, LEC, timing constraints, and low-power design.
• Exposure to Cadence Genus, Xcelium, JasperGold, and Conformal is preferred.
• Experience with standard interfaces such as AMBA AXI/AHB/APB, PCIe, DDR, Ethernet, or similar protocols is advantageous.

Common Requirements

• B.E./B.Tech./M.E./M.Tech. in Electronics, Electrical, VLSI, or a related discipline.
• Minimum 6 years of relevant hands-on experience.
• Experience with at least one production ASIC/SoC project or tape-out.
• Strong debugging, problem-solving, and technical communication skills.
• Scripting knowledge in Tcl, Python, Perl, or Shell is advantageous.
• Ability to collaborate across RTL, DV, DFT, STA, physical design, and sign-off teams.

Candidates interested in exploring these opportunities may share the following on email ID [email removed]

• Updated rsum
• Relevant role/domain
• Total and relevant experience
• Cadence tools used
• Technology nodes worked on
• Block, subsystem, or full-chip experience
• Current and preferred location
• Current and expected compensation
• Notice period/earliest joining date