RTL Verification Lead

Job Title: RTL Design Lead - 10-12 Yrs

Experience required: 10-12 years

Location: Bangalore

No. Of positions: 1

Work Mode: Onsite(all 5 days)

Education: Bachelors and/or Masters in Electronic engineering

• Verilog, system verilog, UVM
• IP level TB component development
• Mastery in EDA tools (Verdi,vcs) etc

• Comfortable in scripting for automation
• AI tools usage
• Experience in digital+analog verification

• Scope: Owns IP and top-level ASIC verification for complex SerDes subsystems.
• Domain: Verifies digital RTL integrated with analog behavioral models using SystemVerilog/UVM.
• Alignment: Ensures seamless functionality across digital, analog, and firmware boundaries.
• Metrics: Drives testbench architecture and test planning to achieve coverage closure.

• Spec Review: Analyze design specs and collaborate with designers to align test plans.
• Testbench Development: Build or upgrade UVM testbenches, write tests, and close coverage.
• Cross-Team Integration: Work with RTL, analog, and firmware teams to bridge design gaps and verify system-level interfaces.
• Behavioral Model Verification: Validate subsystem functionality including analog model and firmware interactions in the digital testbench.
• Productivity: Leverage approved automation and AI tools to accelerate debugging and triage.