RTL Integration Engineer - PCIe Gen5 To Gen8 (BB812FI RM 4549)
Sourceright Technologies · Bengaluru · onsite · Posted today
Undisclosed12–17 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Position: RTL Integration Engineer - PCIe Gen5 to Gen8 (BB812FI RM 4549)
Key skills: PCIe Gen5+ controller and PHY integration, PCIe protocol layers (TL/DL/PHY), LTSSM, TLP/DLLP, flow control, replay, PIPE interface, multi-clock design, CDC, reset sequencing, and AXI/APB-based SoC integration.
Must have silicon-proven PCIe Gen5+ experience; exposure to PCIe Gen6 FLIT-mode architecture is strongly preferred.
Preferred exposure: Chiplet/multi-die SoCs, CXL 2.x/3.x, retimer/redriver integration, post-silicon debug and bring-up, ASPM/low-power integration, RAS/AER, and IDE/link-level security.
Role Overview
We are looking for a highly experienced RTL Integra on Engineer to lead PCIe Gen5 and beyond (Gen6/Gen7/Gen8) controller and PHY integra on for advanced SoC and chiplet-based designs. The role requires deep PCIe protocol knowledge, strong RTL/SoC integra on exper se, and hands-on experience taking designs from integra on through silicon bring-up readiness.
We are looking for a highly experienced RTL Integra on Engineer to lead PCIe Gen5 and beyond (Gen6/Gen7/Gen8) controller and PHY integra on for advanced SoC and chiplet-based designs. The role requires deep PCIe protocol knowledge, strong RTL/SoC integra on exper se, and hands-on experience taking designs from integra on through silicon bring-up readiness.
Key Responsibilities
- Integrate PCIe Gen5+ controllers and PHYs into complex SoC architectures
- Own end-to-end RTL integra on, including parameteriza on, clocking, reset, and CSR integra on
- Ensure correct implementa on of PCIe protocol layers (TL/DL/PHY) and LTSSM behavior
- Manage speed and width change, recovery, and reset scenarios across genera ons
- Drive PIPE (4.x / 5.x) PHY interface integra on, including power-state and latency alignment
- Implement robust error handling, replay logic support, and AER repor ng paths
- Op mize performance, latency, and power across mul ple VCs and traffic classes
- Collaborate with DV, PHY, firmware, and so ware teams to ensure compliance and bring-up
readiness - Support debug and silicon bring-up through visibility hooks and instrumenta on
Required Technical Skills
- Strong hands-on experience with PCIe Gen5 and above RTL integra on
- Deep understanding of PCIe architecture (Root Complex, Endpoint, Switch)
- Exper se in LTSSM states, transi ons, and recovery mechanisms
- Solid knowledge of TLP/DLLP formats, flow control, replay, and ordering rules
- Experience with PIPE interfaces and PHY interac on (rate/width change, power states)
- Proven skills in mul -clock design, CDC, and reset sequencing
- Familiarity with ASPM (L0s, L1, L1.1, L1.2) and low-power integra on
- Strong understanding of error handling, RAS, and AER capability integra on
- Experience integra ng PCIe into AXI/APB-based SoC fabrics
Gen-Specific Expecta ons
- Gen5: 32 GT/s NRZ opera on, ght ming margins, EQ awareness
- Gen6: FLIT-mode architecture, PAM4 signaling, FEC/CRC, PHY latency budge ng
- Gen7/Gen8: Scalable RTL, re mer/chiplet awareness, reliability and RAS focus
Experience Qualifica ons
- 8-12+ years of experience in high-speed interface RTL integra on
- Silicon-proven PCIe Gen5+ experience is mandatory
- Exposure to PCIe Gen6 FLIT-mode strongly preferred
- Experience with chiplet-based or mul -die SoCs is a plus
Preferred differen ators
- CXL 2.x / 3.x awareness
- Re mer/redriver integra on exposure
- Post-silicon debug and bring-up experience
- Security concepts (IDE, link-level protec on)
Job Category: Others
Job Type: Full Time
Job Location: Bangalore
Experience: 8-12 Years
Notice period: immediate joiners
This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Sourced from naukri
Skills
CdcSOCoperaFirmwareIdehooksPCIEEndpointCSRError HandlingDebugArchitecturecompliance