RTL Design Manager

The Role

• AMD is seeking a capable and motivated SOC Design Manager to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices
• You will manage team working on design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products
• This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis.
• You will also contribute to definition/evolution of IP/SOC Design methodologies and processes for future projects

The Person

• Successful candidate will have an SOC/ASIC Design background, team/project management experience, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution

Key Responsibilities

• Team management (hiring, coaching, reviewing and retaining engineers)
• Project Planning
• Tracking Project Execution and reporting of key metrics
• Managing Design reviews around feature and quality
• Retrospectives and project wind-down
• Crossfunctional stakeholder management (marketing, architecture, verification, physical design, chip integration, applications, methodology experts, management)
• Participate in tapeout checklists and reviews
• Improve processes for team through AI adoption and traditional automation

Required Experience

• Engineering
  • Digital design and experience with RTL design in Verilog/System Verilog
  • Solid understanding of DFT technologies and some experience with execution of DFT flows
  • Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
  • Experience in specifying timing constraints with several clock domains and modes
  • Basic experience with Synopsys Design Compiler and Primetime
  • Experience designing with multiple power domains and islands using UPF
  • TCL, Python, Perl scripting
  • Version control systems such as Perforce, IC Manage or Git
  • Fluent in working with Linux and Windows environments
• Leadership/Management
  • Strong verbal and written communication skills
  • Ability to organize and present complex technical information
  • Project planning and management of execution from Microarchitecture to Timing Closure with engineers in multiple timezones
  • Team building experience

Academic Credentials and Experience

• Bachelors or Masters degree in Electrical Engineering with 12+ years of experience.

Disclaimer: This job posting and Location has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.