BENGALURU · FULLTIME

RTL Design Engineer

QTiMinds Private Limited

Bengaluru · onsite · Posted 13d ago

Sourced from Foundit

Not disclosed3–8 yrsfulltimeBengaluru

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Section · 01

About this role

Description

We are seeking a skilled RTL Design Engineer to join our dynamic team in India. The ideal candidate will have extensive experience in RTL design and a strong understanding of digital circuit design principles. You will be responsible for developing and implementing RTL code, optimizing designs, and collaborating with verification teams to ensure the highest quality of digital products.

Responsibilities

Design and implement RTL code for digital circuits using VHDL/Verilog.
Optimize designs for performance, area, and power consumption.
Collaborate with verification teams to ensure design correctness and functionality.
Participate in design reviews and provide constructive feedback.
Conduct synthesis and timing analysis of digital designs.
Debug and resolve design issues throughout the development process.

Skills and Qualifications

Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field.
3-8 years of experience in RTL design and verification.
Proficiency in VHDL/Verilog and SystemVerilog.
Strong understanding of digital design principles and methodologies.
Experience with synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).
Familiarity with simulation tools (e.g., ModelSim, QuestaSim).
Knowledge of FPGA and ASIC design flows.
Ability to work in a team-oriented environment and communicate effectively.

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Section · 02

Skills

physical designtiming analysisVerilogSystem VerilogFPGAVHDLASIC DesignLow-Power Designverification methodologiesSynthesis Tools

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Description

Responsibilities

Design and implement RTL code for digital circuits using VHDL/Verilog.

Optimize designs for performance, area, and power consumption.

Collaborate with verification teams to ensure design correctness and functionality.

Participate in design reviews and provide constructive feedback.

Conduct synthesis and timing analysis of digital designs.

Debug and resolve design issues throughout the development process.

Skills and Qualifications

Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field.

3-8 years of experience in RTL design and verification.

Proficiency in VHDL/Verilog and SystemVerilog.

Strong understanding of digital design principles and methodologies.

Experience with synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).

Familiarity with simulation tools (e.g., ModelSim, QuestaSim).

Knowledge of FPGA and ASIC design flows.

Ability to work in a team-oriented environment and communicate effectively.