RTL Design Engineer

Analyze specifications and develop micro-architecture for digital IPs and subsystems.

Design and implement RTL using Verilog/ System Verilog.

Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness.

Support SoC/IP integration activities.

Participate in design reviews and technical discussions.

Collaborate with verification teams to resolve design issues and achieve quality sign-off.

Support FPGA prototyping and silicon bring-up activities as required.

Prepare and maintain design documentation.