RTL Design Engineer

The Role

This exciting position in AMD's Silicon IP solutions SOC group will provide the individual with an opportunity to demonstrate strong technical leadership across the design hierarchy from architecture to Productization. Join us in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by delivering the complex IP Solutions for multiple market segments.

As an MTS you will work as part of a team responsible for all phases of product development including product definition and delivery. Member Technical Staff is expected to participate in and lead many aspects of a technical project including: thorough understanding of IP architectural definition, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization ASICization.

This position requires an individual to be creative, team-oriented, technology savvy, able to lead large cross-functional teams, comfortable and willing to provide regular updates to management chain during the project execution.

The Person

You have a passion for modern, complex hardware and IP architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

A major part of your responsibility will be to participate in and take a lead technical role in most of the phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation and support including:

• Define u-architecture from the architecture definition
• Evaluating and executing design and development plans for IPs
• RTL design, IP Integration documentation
• Participating in and acting as a senior technical reviewer for various u-architecture and implementation reviews within the development organization
• Working with stakeholders to develop comprehensive testing plans including Compliance and Interop testing
• Critically Review and provide feedback on the Design Implementations and Verification plans
• Acting as technical mentor to junior engineers

Preferred Experience

• A minimum of 8 years of experience is required.
• Proven experience in Silicon IP development process, methodologies, Design for Test methodologies
• Experience with Verilog RTL design, VCS simulation tool, Perl/Shell scripting
• Proven experience in contributing to complex silicon tapeouts
• Detailed understanding and proven track record of developing any of the leading edge PCIe, Full featured DMAs, NVMe based Storage IP, networking IP solutions such as Ethernet, TCP/IP, RDMA IPs.
• Strong oral and written communication skills are essential
• The ideal candidate will be a proactive contributor to the RTL design methodologies
• Ability to work on complex issues where analysis situations or data requires an in-depth evaluation of variable factors.
• To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups.

Academic Credentials

• A Bachelor of Science Degree in Electrical Engineering or Computer Science, a master s degree or equivalent experience is required.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.