CA
RTL Design Engineer
clarus advisers · Hyderabad · onsite · Posted 51d ago
Not disclosed4–6 yrsfulltimeSourced from
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About this role
Company Overview
Our client is a Semiconductor MNC
Position Overview
RTL Design Engineer/Senior Engineer
Responsibilities
Our client is a Semiconductor MNC
Position Overview
RTL Design Engineer/Senior Engineer
Responsibilities
- Drive SOC Assembly and design chip level functions for SOCs.
- Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.
- Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.
- Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
- Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them.
- 4+ years of proven experience in chip design, specializing in SOC integration and design automation. Padring and fuse/floorsweep design experience is a bonus.
- Experience in RTL design (Verilog), System-On-Chip design/implementation flow.
- Strong coding skills in Perl, Python, or other industry-standard scripting languages.
- Exposure to various Chip Design Functions to be able to collaborate and solve complex multi-functional problems.
- Background in SOC Verification, Synthesis, Physical design and DFT is a bonus.
- Experience in RTL Build flows and Makefiles is a plus.
- Excellent analytical and problem-solving skills.
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Skills
Chip Design Functionsphysical designsynthesisPerlVerilogSOC VerificationRTL DesignDFTmakefilesRTL Build flowsSystem-On-Chip design implementation flowPython